Nascent persistent memory (PM) technologies promise the performance of DRAM with the durability of disk, but how best to integrate them into programming systems remains an open question. Recent work extends language memory models with a persistency model prescribing semantics for updates to PM. These semantics enable programmers to design data structures in PM that are accessed like memory and yet are recoverable upon crash or failure. Alas, we find the semantics and performance of existing approaches unsatisfying. Existing approaches require high-overhead mechanisms, are restricted to certain synchronization constructs, provide incomplete semantics, and/or may recover to state that cannot arise in fault-free execution.
We propose persistency semantics that guarantee failure atomicity of synchronization-free regions (SFRs) - program regions delimited by synchronization operations. Our approach provides clear semantics for the PM state recovery code may observe and extends C++11's "sequential consistency for data-race-free" guarantee to post-failure recovery code. We investigate two designs for failure-atomic SFRs that vary in performance and the degree to which commit of persistent state may lag execution. We demonstrate both approaches in LLVM v3.6.0 and compare to a state-of-the-art baseline to show performance improvement up to 87.5% (65.5% avg).
Wed 20 Jun Times are displayed in time zone: (GMT-04:00) Eastern Time (US & Canada) change
|11:00 - 11:25|
Vaibhav GogteUniversity of Michigan, USA, Stephan DiestelhorstARM Research, UK, William WangArm Research, UK, Satish NarayanasamyUniversity of Michigan, Peter M. ChenUniversity of Michigan, USA, Thomas F. WenischUniversity of Michigan, USAMedia Attached
|11:25 - 11:50|
Shoaib AkramGhent University, Jennifer B. SartorVrije Universiteit Brussel, Kathryn S McKinleyGoogle, Lieven EeckhoutGhent University, BelgiumMedia Attached
|11:50 - 12:15|
Chit-Kwan LinIntel Labs, n.n., Andreas WildIntel Labs, n.n., Tsung-Han LinIntel Labs, n.n., Gautham N. ChinyaIntel Labs, n.n., Mike DaviesIntel Labs, n.n., Hong WangIntel Labs, n.n.Media Attached