For decades, Moore’s Law and its partner Dennard Scaling have driven technology trends that have enabled exponential performance improvements in computer systems at manageable power dissipation. With the slowing of Moore/Dennard improvements, designers have turned to a range of approaches for extending scaling of computer systems performance and power efficiency. These include specialized accelerators and heterogeneous parallelism. Unfortunately, the scaling gains afforded by these techniques come at the expense of degraded hardware-software abstraction layers, increased complexity at the hardware-software interface, and increased challenges for software reliability, interoperability, and performance portability. As the role of the Instruction Set Architecture (ISA) interface shifts rapidly, new opportunities and challenges exist for hardware, software, language and tool designers in this “Post-Instruction Set Architecture” era of shifting abstractions. The talk will cover a range of design opportunities and challenges, with a particular emphasis on my group’s recent work on verification methods for memory models in hardware-software systems.