Thu 21 Jun 2018 11:25 - 11:50 at Grand Ballroom AB - Multicore and More Chair(s): Yannis Smaragdakis

Going beyond a certain number of cores in modern architectures requires an on-chip network more scalable than conventional buses. However, employing an on-chip network in a manycore system (to improve scalability) makes the latencies of the data accesses issued by a core non-uniform. This non-uniformity can play a significant role in shaping the overall application performance. This work presents a novel compiler strategy which involves exposing architecture information to the compiler to enable an optimized computation-to-core mapping. Specifically, we propose a compiler-guided scheme that takes into account the relative positions of (and distances between) cores, last-level caches (LLCs) and memory controllers (MCs) in a manycore system, and generates a mapping of computations to cores with the goal of minimizing the on-chip network traffic. The experimental data collected using a set of 21 multi-threaded applications reveal that, on an average, our approach reduces the on-chip network latency in a 6x6 manycore system by 38.4% in the case of private LLCs, and 43.8% in the case of shared LLCs. These improvements translate to the corresponding execution time improvements of 10.9% and 12.7% for the private LLC and shared LLC based systems, respectively.

Thu 21 Jun

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11:00 - 12:15
Multicore and MorePLDI Research Papers at Grand Ballroom AB
Chair(s): Yannis Smaragdakis University of Athens
11:00
25m
Talk
Spatial: A Language and Compiler for Application Accelerators
PLDI Research Papers
David Koeplinger Stanford University, USA, Matthew Feldman Stanford University, USA, Raghu Prabhakar Stanford University, USA, Yaqi Zhang Stanford University, USA, Stefan Hadjis Stanford University, USA, Ruben Fiszel EPFL, Switzerland, Tian Zhao Stanford University, Luigi Nardi Stanford University, Ardavan Pedram Stanford University, USA, Christos Kozyrakis Stanford University, USA, Kunle Olukotun Stanford University
Media Attached
11:25
25m
Talk
Enhancing Computation-to-Core Assignment with Physical Location Information
PLDI Research Papers
Orhan Kislal Pennsylvania State University, USA, Jagadish Kotra Pennsylvania State University, USA, Xulong Tang Penn State, Mahmut Taylan Kandemir University of Pennsylvania, Myoungsoo Jung Yonsei University, South Korea
Media Attached
11:50
25m
Talk
SWOOP: Software-Hardware Co-design for Non-speculative, Execute-Ahead, In-Order Cores
PLDI Research Papers
Kim-Anh Tran Uppsala University, Sweden, Alexandra Jimborean Uppsala University, Trevor E. Carlson National University of Singapore, Konstantinos Koukos Uppsala University, Sweden, Magnus Själander Norwegian University of Science and Technology (NTNU), Stefanos Kaxiras Uppsala University, Sweden
Media Attached